Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells. An exemplary NAND Flash architecture is described by Takeuchi et al., in “A Double Level VTH Select Gate Array Architecture for Multi-Level NAND Flash Memories,” Digest of Technical Papers, 1995 Symposium on VLSI Circuits, Jun. 8-10, 1995, pages 69-70, which is incorporated herein by reference.
In many memory devices, data is stored in programming levels that are represented by positive threshold voltages (the minimal voltage that needs to be applied to the gate of the cell in order to cause the cell to conduct), and erased cells are set to a level that is represented by a negative threshold voltage. Several methods for sensing negative threshold voltages are known in the art, such as for verifying that cells have been properly erased.
For example, U.S. Pat. No. 7,031,210, whose disclosure is incorporated herein by reference, describes a method of measuring threshold voltages in a NAND Flash memory device. A test voltage is applied to a word line of selected memory cells to measure a distribution profile of threshold voltages of memory cells. A voltage summing up a pass voltage and an operation voltage is applied to word lines of deselected cells. The operation voltage is applied to a well and a common source line. A voltage summing up a pre-charge voltage and the operation voltage is applied to a bit line. Then, a voltage variation on the bit line can be detected to measure a threshold voltage of a memory cell. A negative threshold voltage can be measured by applying a positive voltage with reference to a voltage, as the threshold voltage of the memory cell, set by subtracting the operation voltage from the test voltage in accordance with the bit line voltage variation.
U.S. Pat. No. 6,288,944, whose disclosure is incorporated herein by reference, describes a NAND-type nonvolatile memory. The memory includes a sense circuit having a constant current supply source connected to a bit line to which memory cells are connected, and a sense transistor for sensing potential at the connection point thereof. The memory further includes a first reference potential on the opposite side from the bit line of the memory cells, and a second reference potential to which the source of the sense transistor is connected. During erase verification operations, the first reference potential and the second reference potential are controlled to a predetermined positive potential. By controlling the first reference potential to the positive potential, the control gate level of a memory cell can be equivalently brought to an erase-verify level (which is negative). By further controlling the second reference potential of the sense transistor to a positive potential, the equivalent threshold voltage of the sense transistor can be increased, or the equivalent trip level of the sense inverter increased.
U.S. Pat. No. 5,696,717, whose disclosure is incorporated herein by reference, describes a memory device that includes an array of NAND strings containing a plurality of memory cells and sense amplifiers for determining whether the memory cells have been properly erased and programmed during respective erase and program verification modes of operation. The memory includes an erase voltage adjusting circuit for setting a limit on a range of acceptable erase threshold voltages and a program voltage adjusting circuit for setting a limit on a range of acceptable program threshold voltages. The sense amplifier determines, during an erase verification operation, whether a memory cell in a NAND string has been erased to have a threshold voltage within a range of acceptable erase threshold voltages. The range of acceptable erase threshold voltages typically has an upper limit less than a predetermined reference potential (e.g., ground).